Problem in implementation stage: using clock source as an input signal.
Xilinx XAPP132: Using the Virtex Delay-Locked Loop, Application ...
Optimizing Clock Resources in FPGAs - Circuit Cellar
Virtex-6 CXT Datasheet by Xilinx Inc. | Digi-Key Electronics
Xilinx XAPP704 Virtex-4 High-Speed Single Data Rate LVDS ...
Breaking all the rules to create an arbitrary clock signal
Sub-optimal placement for a clock-capable IO pin and MMCM pair
Clock Signal Management: Clock Resources of FPGAs - Technical Articles
Xilinx FPGA Overview | DigiKey
FPGA Board with Xilinx Spartan-7
Step 1: Create the Vivado Hardware Design and Generate XSA — Vitis™ Tutorials 2021.1 documentation
Step 1: Create the Vivado Hardware Design and Generate XSA — Vitis™ Tutorials 2021.1 documentation
MicroZed Chronicles: Thinking about Clocks.
How to find clock compatible pin
ZCU1285 Characterization Board Guide Datasheet by Xilinx Inc. | Digi-Key Electronics
Clock capable pin can be used as Inout for clock ?
Spartan-7 FPGAs Datasheet by Xilinx Inc. | Digi-Key Electronics
Xilinx XAPP225 Data to Clock Phase Alignment, Application Note
Ultrascale+ Clocking proiblem (IBUFDS -> BUFG, BUFGCE_DIV -> SERDES)
Widget
clock capable output pins in XC7K325T-2FBG900C
ADC clock to MMcM routing problem ?
Versal ACAP Clocking Resources Architecture Manual
Clock capable pin can be used as Inout for clock ?
Artix-7 FPGAs Datasheet by Xilinx Inc. | Digi-Key Electronics
Optimizing Clock Resources in FPGAs - Circuit Cellar
![Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair - FPGA - Digilent Forum](https://content.invisioncic.com/f319528/monthly_2019_04/Arty-A7-100-GSWM-3.jpg.e7a4a1429b26dfe923ec7a164a739693.jpg "Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair - FPGA - Digilent Forum")
Place 30-172] Sub-optimal placement for a clock-capable IO pin and PLL pair - FPGA - Digilent Forum
